Pinned

1. pentaRV pentaRV Public

   pentaRV consists of a 5 stage pipelined Rv32I core and the project plans to implement a RISC-V based SOC .

   Verilog 2

2. nandToTetris nandToTetris Public

   My project assignments for Nand to Tetris course on Coursera

   Hack 1

3. learn-cocotb/assignment-1-xor-verification-Rohan7Gupta learn-cocotb/assignment-1-xor-verification-Rohan7Gupta Public

   assignment-1-xor-verification-Rohan7Gupta created by GitHub Classroom

   Python

4. smitrv smitrv Public

   Verilog 2

5. Matlab Matlab Public

   MATLAB 1

6. neilit_course neilit_course Public

   Verilog