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  • 09:35 (UTC +02:00)

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  1. lowRISC/opentitan lowRISC/opentitan Public

    OpenTitan: Open source silicon root of trust

    SystemVerilog 2.4k 698

  2. lowRISC/ibex lowRISC/ibex Public

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1.2k 479

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    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog 929 239

  4. pulp-platform/hero pulp-platform/hero Public

    Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …

    SystemVerilog 87 24

  5. memora-rs memora-rs Public

    Memora: Build Artifact Cache for Git Repositories

    Rust 8 3