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Pull requests: ucb-bar/chipyard

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Pull requests list

Bump CDE/diplomacy to fix messy .gitignores changelog:omit
#1865 opened Apr 25, 2024 by jerryz123 Loading…
16 tasks
Add legacy SFC emission with firrtl2 changelog:added
#1863 opened Apr 24, 2024 by jerryz123 Loading…
16 tasks
Remove tapeout.GenerateModelStageMain changelog:removed
#1860 opened Apr 23, 2024 by jerryz123 Loading…
16 tasks
Remove legacy SFC flags changelog:removed
#1859 opened Apr 23, 2024 by jerryz123 Loading…
16 tasks
Support Chisel6 for RTL-sim/VLSI/FPGA flows changelog:added
#1854 opened Apr 19, 2024 by jerryz123 Loading…
16 tasks
[WIP] Dmi Bridge hacking
#1852 opened Apr 18, 2024 by soohyuk-cho Draft
16 tasks
Add Verilog blackbox TLDevice example changelog:added
#1827 opened Mar 17, 2024 by jerryz123 Loading…
16 tasks
[WIP] Integrate ReRoCC changelog:added
#1783 opened Feb 5, 2024 by jerryz123 Loading…
16 tasks
FireSim DMI Bridge changelog:added
#1619 opened Oct 10, 2023 by abejgonzalez Loading…
2 of 16 tasks
Force specific locale changelog:fixed
#1528 opened Jun 19, 2023 by jerryz123 Loading…
1 of 16 tasks
[WIP] Add singleclock broadcast clockbinder
#1461 opened May 5, 2023 by jerryz123 Draft
16 tasks
[WIP] Many-core config
#1404 opened Mar 16, 2023 by jerryz123 Draft
16 tasks
Add rocc-to-noc example changelog:added
#1380 opened Mar 6, 2023 by jerryz123 Loading…
7 of 16 tasks
Improve readability for vcu118 fpga code
#1274 opened Nov 23, 2022 by Lorilandly Draft
5 of 16 tasks
Add support for Digilent Genesys 2 board
#784 opened Feb 2, 2021 by yqszxx Loading… 1.8.0
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