Haskell to VHDL/Verilog/SystemVerilog compiler

Hardware Description Languages

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

SystemRDL 2.0 language compiler front-end

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

A core language for rule-based hardware design 🦑

Fearless hardware design

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…

ACT hardware description language and core tools.

Control and status register code generator toolchain

VHDL Guide

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

A place to keep my synthesizable verilog examples.

🔁 elastic circuit toolchain

📚Repositório da Disciplina INE5406 - Sistemas Digitais

5 Day TCL begginer to advanced training workshop by VSD

This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.

Python Manufacturing Utility or "mupy" is a powerful new digital-twin technology. In it's essence, a new way to think about design, physical hardware, advanced assemblies, innovative technologies, or most generally, system design.