A FPGA friendly 32 bit RISC-V CPU implementation

⭐ ⭐ Distributed tcpdump for cloud native environments ⭐ ⭐

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The SOC Analysts all-in-one CLI tool to automate and speed up workflow.

The Ultra-Low Power RISC-V Core

A collection of sources of documentation, as well as field best practices, to build/run a SOC

The extensible bootloader for embedded system with application engine, write once, run everywhere.

学习安全运营的记录 | The knowledge base of security operation

Open source security data pipelines.

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

一些常见的安全检测规则及事件

SIEM Tactics, Techiques, and Procedures

Vitis_Accel_Examples

A collection of PowerShell modules designed for artifact gathering and reconnaisance of Windows-based endpoints.

MasterParser is a powerful DFIR tool designed for analyzing and parsing Linux logs

Awesome list of keywords and artifacts for Threat Hunting sessions

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Code generation tool for control and status registers

Microsoft Sentinel SOC Operations